As technology progresses, integrated circuits, such as memory arrays, pixel arrays and so on, have become ever denser and ever smaller. As the arrays incorporate devices of smaller feature sizes, effects of parasitic capacitance, cross coupling capacitance, resistance, and/or inductance from the physical implementation of the devices and/or interconnections of the devices are more pronounced. To simulate behaviors of a physically implemented array, parasitic extraction is performed on a layout of the array and post layout simulation is performed on a netlist of the array back-annotated with the parasitic information.